EZ80L92AZ020SC00TR Zilog, EZ80L92AZ020SC00TR Datasheet - Page 11

• Manufacturer Part Number: EZ80L92AZ020SC00TR
• Description: IC EZ80 MPU 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ020SC00TR

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 20MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: EZ80L92AZ020SC00T

Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU
PS013014-0107
Pin No
1
2
3
4
5
6
Symbol
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
Function
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Signal Direction
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
Description
Product Specification
Architectural Overview
5