EZ80L92AZ020SC00TR Zilog, EZ80L92AZ020SC00TR Datasheet - Page 168

• Manufacturer Part Number: EZ80L92AZ020SC00TR
• Description: IC EZ80 MPU 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ020SC00TR

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 20MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: EZ80L92AZ020SC00T

PS013014-0107
ZDI Clock and Data Conventions
ZDI START Condition
The two pins used for communication with the ZDI block are ZDI Clock pin (ZCL) and
ZDI Data pin (ZDA). On eZ80L92 MCU, the ZCL pin is shared with the TCK pin while
the ZDA pin is shared with the TDI pin. The ZCL pin and ZDA pin functions are only
available when the on-chip instrumentation is disabled and the ZDI is therefore enabled.
For general data communication, the data value on the ZDA pin changes only when ZCL
is Low (0). The only exception is the ZDI START bit, which is indicated by a High-to-
Low transition (falling edge) on the ZDA pin while ZCL is High.
Data is shifted in and out of ZDI, with the most significant bit (bit 7) of each byte being
first in time, and the least significant bit (bit 0) last in time. The information is transferred
between the master and the slave in 8-bit (single-byte) units. Each byte is transferred with
nine clock cycles: eight to shift the data, and the ninth for internal operations.
All the ZDI commands are preceded by a ZDI START signal, which is a High-to-Low
transition of ZDA when ZCL is High. The ZDI slave on the eZ80L92 continually monitors
the ZDA and ZCL lines for the START signal and does not respond to any command until
this condition is met. The master pulls ZDA Low, with ZCL High, to indicate the
beginning of a data transfer with the ZDI block.
ZDI START signal prior to writing and reading the data, respectively. A Low-to-High
transition of ZDA while the ZCL is High produces no effect.
Data is shifted in during a Write to the ZDI block on the rising edge of ZCL, as illustrated
in
ZCL as illustrated in
the ninth cycle and holds the ZCL signal High.
ZDA
ZCL
Figure
37. Data is shifted out during a Read from the ZDI block on the falling edge of
Start Signal
Figure
38. When an operation is completed, the master stops during
ZDI Data In
Figure 37. ZDI Write Timing
(Write)
Figure 37
ZDI Data In
(Write)
and
Figure 38
Product Specification
ZiLOG Debug Interface
illustrate a valid
eZ80L92 MCU
162