EZ80L92AZ020SC00TR Zilog, EZ80L92AZ020SC00TR Datasheet - Page 117

• Manufacturer Part Number: EZ80L92AZ020SC00TR
• Description: IC EZ80 MPU 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ020SC00TR

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 20MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: EZ80L92AZ020SC00T

PS013014-0107
Write attributes, reset conditions, and bit descriptions of all of the UART registers are pro-
vided in this section.
UART Transmit Holding Registers
If less than eight bits are programmed for transmission, the lower bits of the byte written
to this register are selected for transmission. The transmit FIFO is mapped at this address.
You can write up to 16 bytes for transmission at one time to this address if the FIFO is
enabled by the application. If the FIFO is disabled, this buffer is only one byte deep.
These registers share the same address space as the UARTx_RBR and UARTx_BRG_L
registers. See
Table 54. UART Transmit Holding Registers (UART0_THR = 00C0h, UART1_THR =
UART Receive Buffer Registers
The bits in this register reflect the data received. If less than eight bits are programmed for
receive, the lower bits of the byte reflect the bits received whereas upper unused bits are 0.
The receive FIFO is mapped at this address. If the FIFO is disabled, this buffer is only one
byte deep.
These registers share the same address space as the UARTx_THR and UARTx_BRG_L
registers. See
Bit
Reset
CPU Access
Note: W = Write only.
Bit
Position
[7:0]
T
x
D
00D0h)
Table
Table
00h–FFh Transmit data byte.
Value
54.
55.
W
X
7
Description
W
X
6
W
X
5
Universal Asynchronous Receiver/Transmitter
W
X
4
W
X
3
Product Specification
W
X
2
eZ80L92 MCU
W
X
1
W
X
0
111