EZ80L92AZ020SC00TR Zilog, EZ80L92AZ020SC00TR Datasheet - Page 92

• Manufacturer Part Number: EZ80L92AZ020SC00TR
• Description: IC EZ80 MPU 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ020SC00TR

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 20MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: EZ80L92AZ020SC00T

PS013014-0107
Note:
Timer Reload Registers—High Byte
The Timer Reload Register—High Byte, detailed in
byte (MSB) of the 2-byte timer reload value. In CONTINUOUS mode, the timer reload
value is reloaded into the timer upon end-of-count. When RST_EN (TMRx_CTL[1]) is set
to 1 to enable the automatic reload and restart function, the timer reload value is written to
the timer on the next rising edge of the clock.
The Timer Data registers and Timer Reload registers share the same address space.
Table 36. Timer Reload Registers—High Byte (TMR0_RR_H = 0082h,
TMR1_RR_H = 0085h, TMR2_RR_H = 0088h, TMR3_RR_H = 008Bh,
TMR4_RR_H = 008Eh, or TMR5_RR_H = 0091h)
Timer Input Source Select Register
The Timer Input Source Select register, detailed in
grammable Reload Timer 0–3 (TMR0, TMR1, TMR2, TMR3). Event frequency must be
less than one-half of the system clock frequency. When configured for event inputs
through the port pins, the Timers decrement on the fifth system clock rising edge follow-
ing the rising edge of the port pin.
Bit
Reset
CPU Access
Note: W = Write only.
Bit
Position
[7:0]
TMRx_RR_H
00h–FFh These bits represent the High byte of the 2-byte timer
Value
W
7
0
Description
reload value, {TMRx_RR_H[7:0], TMRx_RR_L[7:0]}. Bit 7
is bit 15 (msb) of the 16-bit timer reload value. Bit 0 is bit 8
of the 16-bit timer reload value.
W
6
0
W
5
0
Table
W
Table
4
0
37, sets the input source for Pro-
36, stores the most significant
W
3
0
Programmable Reload Timers
Product Specification
W
2
0
eZ80L92 MCU
W
1
0
W
0
0
86