EZ80L92AZ020SC00TR Zilog, EZ80L92AZ020SC00TR Datasheet - Page 154

IC EZ80 MPU 100LQFP

EZ80L92AZ020SC00TR

Manufacturer Part Number
EZ80L92AZ020SC00TR
Description
IC EZ80 MPU 100LQFP
Manufacturer
Zilog
Datasheet

Specifications of EZ80L92AZ020SC00TR

Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
20MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
EZ80L92AZ020SC00T

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80L92AZ020SC00TR
Manufacturer:
Zilog
Quantity:
10 000
PS013014-0107
Table 78. I
If 10-bit addressing is being used, the slave is first addressed using the full 10-bit address
plus the Write bit. The master then issues a restart followed by the first part of the 10-bit
address again, but with the Read bit. The status code then becomes
responsibility of the slave to remember that it had been selected prior to the restart.
If a repeated START condition is received, the status code is
After each data byte is received, the IFLG is set and one of the status codes listed in
Table 79
Code
48h
38h
68h
78h
B0h
Note: R = Read bit; in essence, the lsb is set to 1.
is in the I2C_SR register.
I
Addr + R
transmitted, ACK not
received
Arbitration lost
Arbitration lost,
SLA+W received,
ACK transmitted
Arbitration lost,
General call addr
received, ACK
transmitted
Arbitration lost,
SLA+R received,
ACK transmitted
2
2 C State
C Master Receive Status Codes (Continued)
MCU Response
For a 7-bit address:
Set STA, clear IFLG
Or set STP, clear IFLG
Or set STA & STP,
clear IFLG
For a 10-bit address:
Write extended address byte
to DATA, clear IFLG
Clear IFLG
Or set STA, clear IFLG
Clear IFLG, clear AAK = 0
Or clear IFLG, set AAK = 1
Same as code 68h
Write byte to DATA,
clear IFLG, clear AAK = 0
Or write byte to DATA,
clear IFLG, set AAK = 1
10h
Next I
Transmit repeated
START
Transmit STOP
Transmit STOP then
START
Transmit extended
address byte
Return to idle
Transmit START when
bus is free
Receive data byte,
transmit NACK
Receive data byte,
transmit ACK
Same as code 68h
Transmit last byte,
receive ACK
Transmit data byte,
receive ACK
Product Specification
instead of
40h
2 C Action
I
2
C Serial I/O Interface
or
48h
08h
. It is the
.
148

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