EZ80L92AZ020SC00TR Zilog, EZ80L92AZ020SC00TR Datasheet - Page 142

• Manufacturer Part Number: EZ80L92AZ020SC00TR
• Description: IC EZ80 MPU 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ020SC00TR

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 20MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: EZ80L92AZ020SC00T

PS013014-0107
SPI Status Register
The SPI Status Read-Only register returns the status of data transmitted using the serial
peripheral interface. Reading the SPI_SR register clears Bits 7, 6, and 4 to a logical 0.
See
Table 72. SPI Status Register (SPI_SR = 00BBh)
Bit
Position
3
CPOL
2
CPHA
[1:0]
Bit
Reset
CPU Access
Note: R = Read Only
Bit
Position
7
SPIF
6
WCOL
5
4
MODF
[3:0]
Table
72.
Value Description
Value Description
0000
00
0
1
0
1
0
1
0
1
0
0
1
Master SCK pin idles in a Low (0) state.
Master SCK pin idles in a High (1) state.
SS must go High after transfer of every byte of data.
SS can remain Low to transfer any number of data bytes.
Reserved.
R
7
0
SPI data transfer is not finished.
SPI data transfer is finished. If enabled, an interrupt is
generated. This bit flag is cleared to 0 by a Read of the
SPI_SR register.
An SPI write collision is not detected.
An SPI write collision is detected. This bit flag is cleared to
0 by a Read of the SPI_SR registers.
Reserved.
A mode fault (multimaster conflict) is not detected.
A mode fault (multimaster conflict) is detected. This bit flag
is cleared to 0 by a Read of the SPI_SR register.
Reserved.
R
6
0
R
5
0
R
4
0
R
3
0
Product Specification
Serial Peripheral Interface
R
2
0
eZ80L92 MCU
R
1
0
R
0
0
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