EZ80L92AZ020SC00TR Zilog, EZ80L92AZ020SC00TR Datasheet - Page 80

IC EZ80 MPU 100LQFP

EZ80L92AZ020SC00TR

Manufacturer Part Number
EZ80L92AZ020SC00TR
Description
IC EZ80 MPU 100LQFP
Manufacturer
Zilog
Datasheet

Specifications of EZ80L92AZ020SC00TR

Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
20MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
EZ80L92AZ020SC00T

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80L92AZ020SC00TR
Manufacturer:
Zilog
Quantity:
10 000
PS013014-0107
Watchdog Timer Operation
Enabling and Disabling the WDT
The Watchdog Timer is disabled upon a system reset (RESET). To enable the WDT, the
application program must set the WDT_EN bit (bit 7) of the WDT_CTL register. When
enabled, the WDT cannot be disabled without a RESET.
Time-Out Period Selection
There are four choices of time-out periods for the WDT—2
clock cycles. The WDT time-out period is defined by the WDT_PERIOD field of the
WDT_CTL register (WDT_CTL[1:0]). The approximate time-out periods for two
different WDT clock sources is listed in
Table 26. Watchdog Timer Approximate Time-Out Delays
RESET Or NMI Generation
Upon a WDT time-out, the RST_FLAG in the WDT_CTL register is set to 1. In addition,
the WDT can cause a RESET or send a nonmaskable interrupt (NMI) signal to the CPU.
The default operation is for the WDT to cause a RESET. It asserts/deasserts on the rising
edge of the clock. The RST_FLAG bit can be polled by the CPU to determine the source
of the RESET event.
If the NMI_OUT bit in the WDT_CTL register is set to 1, then upon time-out, the WDT
asserts an NMI for CPU processing. The RST_FLAG bit can be polled by the CPU to
Clock Source
32.768 kHz Crystal Oscillator
32.768 kHz Crystal Oscillator
32.768 kHz Crystal Oscillator
32.768 kHz Crystal Oscillator
20 MHz System Clock
20 MHz System Clock
20 MHz System Clock
20 MHz System Clock
50 MHz System Clock
50 MHz System Clock
50 MHz System Clock
50 MHz System Clock
Divider Value
Table
2
2
2
2
2
2
2
2
2
2
2
2
18
22
25
27
18
22
25
27
18
22
25
27
26.
Time Out Delay
209.7 ms
83.9 ms*
13.1 ms
5.2 ms*
1024 s
4096 s
8.00 s
0.67 s
2.68 s
128 s
1.68 s
6.71 s
18
, 2
22
Product Specification
, 2
25
, and 2
eZ80L92 MCU
Watchdog Timer
27
system
74

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