MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 126
![IC MPU QUICC 25MHZ 357-PBGA](/photos/6/76/67680/mfg_mpc860_series_sml.jpg)
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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MC68360VR25VL
Manufacturer:
Exar
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Company:
Part Number:
MC68360VR25VL
Manufacturer:
Freescale Semiconductor
Quantity:
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MC68360VR25VLR2
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10 000
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Bus Operation
received BG through the arbitration process, and BGACK must be inactive, indicating that
no other bus master has claimed ownership of the bus.
Figure 4-34 is a flowchart showing the detail involved in bus arbitration for a single device.
This technique allows processing of bus requests during data transfer cycles.
The QUICC has a synchronous arbitration timing mode to reduce the BR to BG delay to one
clock in the idle bus case (see Figure 4-35). Figure 4-36 illustrates the active bus case.
BR is negated at the time that BGACK is asserted. This type of operation applies to a system
consisting of the QUICC and one device capable of bus mastership. In a system having a
number of devices capable of bus mastership, BR from each device can be wire-ORed to
the QUICC. In such a system, more than one bus request could be asserted simultaneously.
BG is negated a few clock cycles after the transition of BGACK. However, if bus requests
are still pending after the negation of BG, the QUICC asserts another BG within a few clock
cycles after it was negated. This additional assertion of BG allows external arbitration cir-
cuitry to select the next bus master before the current bus master has finished using the bus.
The following paragraphs provide additional information about the three steps in the arbitra-
tion process. Bus arbitration requests are recognized during normal processing, HALT
assertion, and when the CPU32+ has halted due to a double bus fault.
4-50
Figure 4-34. Bus Arbitration Flowchart for Single Request
1) ASSERT BG
1) NEGATE BG (AND WAIT FOR
BGACK TO BE NEGATED)
RE-ARBITRATE OR RESUME
TERMINATE ARBITRATION
GRANT BUS ARBITRATION
PROCESSOR OPERATION
QUICC
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
1) EXTERNAL ARBITRATION DETERMINES
2) NEXT BUS MASTER WAITS FOR BGACK
3) NEXT BUS MASTER ASSERTS BGACK
4) BUS MASTER NEGATES BR
1) PERFORM DATA TRANSFERS (READ AND
1) NEGATE BGACK
1) ASSERT BR
NEXT BUS MASTER
TO BE NEGATED
TO BECOME NEW MASTER
WRITE CYCLES) ACCORDING TO THE
SAME RULES THE PROCESSOR USES
ACKNOWLEDGE BUS MASTERSHIP
OPERATE AS BUS MASTER
RELEASE BUS MASTERSHIP
REQUESTING DEVICE
REQUEST THE BUS
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