MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 234
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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CPU32+
5.7.2.3 MOVE INSTRUCTION. The MOVE instruction table indicates the number of clock
periods needed for the processor to calculate the destination EA and to perform a MOVE or
MOVEA instruction. For entries with CEA or FEA, refer to the appropriate table to calculate
that portion of the instruction time.
Destination EAs are divided by their formats (see CPU32 Reference Manual). The total
number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w)
are included in the total clock cycle number. All timing data assumes two-clock reads and
writes.
When using this table, begin at the top and move downward. Use the first entry that matches
both source and destination addressing modes.
5.7.2.4 SPECIAL-PURPOSE MOVE INSTRUCTION. The special-purpose MOVE instruc-
tion table indicates the number of clock periods needed for the processor to fetch, calculate,
and perform the special-purpose MOVE operation on control registers or a specified EA.
Footnotes indicate when to account for the appropriate EA times. The total number of clock
cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in
the total clock cycle number. All timing data assumes two-clock reads and writes.
5-92
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
X = There is one bus cycle for byte and word operands and two bus cycles for long-word oper-
ands. For long-word bus cycles, add two clocks to the tail and to the number of cycles.
Timing is calculated with the CPU32+ in 16-bit mode.
NOTE: For instructions not explicitly listed, use the MOVE CEA , FEA entry. The source
EA is calculated by the calculate EA table, and the destination EA is calculated by the fetch EA
table, even though the bus cycle is for the source EA.
= An # fetch EA time must be added for this instruction: FEA
Rn, Rn
Rn, (Am)
Rn, (Am)
Rn, (Am)
Rn, CEA
#, CEA
FEA , Rn
FEA , (An)
FEA , (An)
FEA , (An)
CEA , FEA
Instruction
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Head
0
0
0
1
2
1
2
2
2
2
2
Tail
0
0
2
1
2
3
2
2
2
2
2
CEA
OPER
6(0/1/X
2(0/1/0)
2(0/1/0)
4(0/1/X)
5(0/1/X)
5(0/1/X)
6(0/1/X)
6(0/1/X)
6(0/1/X)
Cycles
6(0/1/X
6(0/1/X
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