MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 390
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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MC68360VR25VL
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Exar
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Company:
Part Number:
MC68360VR25VL
Manufacturer:
Freescale Semiconductor
Quantity:
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10 000
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Serial Interface with Time Slot Assigner
The TSA also allows two TDM channels to be supported simultaneously. Thus, in its most
flexible mode, the TSA can provide two separate TDM channels, each with an independent
receive and transmit routing assignment and independent sync pulse and clock inputs (see
Figure 7-21). Thus, the TSA can support four, independent, half-duplex TDM sources, two
in reception and two in transmission, using four sync inputs and four clock inputs.
In addition to channel programming, the TSA supports up to four strobe outputs that may be
asserted on a bit basis or a byte basis. These strobes are completely independent from the
channel routing used by the SCCs and SMCs. They are useful for interfacing to other
devices that do not support the multiplexed interface or for enabling/disabling three-state I/
O buffers in a multi-transmitter architecture. (Note that open-drain programming on the
TXDx pins to support a multi-transmitter architecture is programmed in the parallel I/O
block.) These strobes can also be used for generating output waveforms to support such
applications as stepper motor control.
Most TSA programming is accomplished in two SI RAMs, each of size 64
SI RAMs are directly accessible by the host processor in the internal register section of the
QUICC and are not associated with the dual-port RAM. One SI RAM is always used to pro-
7-66
NOTE: SCCs may receive on one TDM and transmit on another (e.g., SCC2 and SCC3).
QUICC
TSA
TDMa
TDMb
Figure 7-21. Dual TDM Channel Example
Freescale Semiconductor, Inc.
TDMa Tx CLOCK
TDMa Rx CLOCK
TDMb Tx CLOCK
TDMb Rx CLOCK
For More Information On This Product,
TDMb Rx SYNC
TDMa Rx SYNC
TDMa Tx SYNC
TDMb Tx SYNC
TDMa Rx
TDMb Rx
TDMa Tx
TDMb Tx
MC68360 USER’S MANUAL
Go to: www.freescale.com
SCC2
SCC3
SMC1
SCC2
SCC2
SCC4
SCC3
SMC1
16 bits. These
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