MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 150
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Manufacturer:
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Part Number:
MC68360VR25VL
Manufacturer:
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CPU32+
5.3 INSTRUCTION SET
The following paragaphs describe the CPU32+ instruction set. A description of the instruc-
tion format, the operands used by the instructions, and a summary of the instructions by cat-
egory are included. Complete programming information is provided in the M68000PM/AD,
M68000 Family Programmer’s Reference Manual.
The CPU32+ instructions include machine functions for all the following operations:
The large instruction set encompasses a complete range of capabilities and, combined with
the enhanced addressing modes, provides a flexible base for program development.
The instruction set of the CPU32+ is very similar to that of the MC68020 (see Table 5-1).
The following M68020 instructions are not implemented on the CPU32+:
The CPU32+ traps on unimplemented instructions or illegal effective addressing modes,
allowing user-supplied code to emulate unimplemented capabilities or to define special-pur-
pose functions. However, Motorola reserves the right to use all currently unimplemented
instruction operation codes for future M68000 core enhancements.
5-8
• Data Movement
• Arithmetic Operations
• Logical Operations
• Shifts and Rotates
• Bit Manipulation
• Conditionals and Branches
• System Control
BFxx
CALLM, RTM — Call Module, Return Module
CAS, CAS2
cpxxx
PACK, UNPK — Pack, Unpack BCD Instructions
15
T1
ENABLE
TRACE
T0
SUPERVISOR/USER
14
STATE
13
S
— Bit Field Instructions (BFCHG, BFCLR, BFEXTS, BFEXTU,
— Compare and Set (Read-Modify-Write Instructions)
— Coprocessor Instructions (cpBcc, cpDBcc, cpGEN, cpRESTORE,
SYSTEM BYTE
12
0
BFFFO, BFINS, BFSET, BFTST)
cpSAVE, cpScc, cpTRAPcc)
Freescale Semiconductor, Inc.
11
For More Information On This Product,
0
Figure 5-5. Status Register
10
I2
PRIORITY MASK
MC68360 USER’S MANUAL
INTERRUPT
Go to: www.freescale.com
9
I1
8
I0
0
7
0
6
(CONDITION CODE REGISTER)
5
0
EXTEND
USER BYTE
4
X
NEGATIVE
3
N
ZERO
2
Z
OVERFLOW
1
V
CARRY
0
C
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