MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 601
![IC MPU QUICC 25MHZ 357-PBGA](/photos/6/76/67680/mfg_mpc860_series_sml.jpg)
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68360VR25VL
Manufacturer:
Exar
Quantity:
160
Company:
Part Number:
MC68360VR25VL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC68360VR25VLR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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The SMCs in UART mode, however, do provide one feature not provided by the regular
SCCs. The SMCs allow a data length option of up to 14 bits; whereas, the SCCs provide a
data length up to 8 bits. See Figure 7-75 for the SMC UART frame format.
7.11.7.3 SMC UART MEMORY MAP. When configured to operate in UART mode, the
QUICC overlays the structure listed in Table 7-5 with the UART-specific parameters
described in Table 7-13.
MAX_IDL. Once a character of data is received on the line, the UART controller begins
counting any idle characters received. If a MAX_IDL number of idle characters is received
before the next data character is received, an idle timeout occurs, and the buffer is closed.
This, in turn, can produce an interrupt request to the CPU32+ core to receive the data from
• Fractional Stop Bits
• Built-In Multidrop Modes
• Freeze Mode for Implementing Flow Control
• Isochronous Operation (1x Clock)
• Interrupts upon Receiving Special Control Characters
• Ability To Transmit Data on Demand using the TODR
• SCCS Register To Determine Idle Status of the Receive Pin
• Other Features for the SCCs as Described in the GSMR
SMTXD
SMCLK
SMC Base + 28
SMC Base + 2A
SMC Base + 2C
SMC Base + 2E
SMC Base +30
SMC Base +32
16
Address
START
BIT
Table 7-13. SMC UART-Specific Parameter RAM
Freescale Semiconductor, Inc.
Figure 7-75. SMC UART Frame Format
For More Information On This Product,
MAX_IDL
R_mask
BRKEC
BRKCR
BRKLN
Name
IDLC
MC68360 USER’S MANUAL
LEAST SIGNIFICANT BIT FIRST
Go to: www.freescale.com
5 TO 14 DATA BITS WITH THE
Width
Word
Word
Word
Word
Word
Word
Maximum Idle Characters
Temporary Idle Counter
Last Received Break Length
Receive Break Condition Counter
Break Count Register (Transmit)
Temporary Bit Mask
Serial Management Controllers (SMCs)
Description
OPTIONAL
PAR.
BIT
(CLOCK NOT TO SCALE)
1 OR 2
STOP BITS
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