MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 737
![IC MPU QUICC 25MHZ 357-PBGA](/photos/6/76/67680/mfg_mpc860_series_sml.jpg)
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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Also, before the interrupt can be processed, the CPU32+ status register (SR) must be pro-
grammed to change the interrupt mask bits from a value of $7 to a value of $0 (or at least a
value lower than the interrupt level desired).
Next, write the PITR bits in the PITR to start the timer and wait for the interrupt.
Step 17: Test the CPM
After the SIM60 is programmed, it is time to begin testing the CPM. In order of increasing
initialization complexity, the following sub-blocks may be tested. See the initialization exam-
ples included in this manual where the blocks are described.
The SPI, SMCs, and SCCs should be tested in loopback mode before attempting to send
and receive data externally.
Step 18: Generate Interrupts with the CPM
When testing interrupts on the CPM, the user should implement this gradually. First, gener-
ate an interrupt with a timer or parallel I/O pin. Then proceed to more complicated interrupt
structures like the serial channels.
Step 19: Enable External Interrupts
The next step is to allow external devices (if any) to interrupt the QUICC. These interrupts
can enter the QUICC through the SIM60 (IRQx pins) or the CPM (parallel I/O pins with inter-
rupt capability).
Dual-Port RAM
Parallel I/O Ports A, B, and C
Baud Rate Generators
Four General-Purpose Timers
RISC Timer Tables
IDMA (without buffer chaining)
SPI (loopback mode test)
IDMA (with buffer chaining)
SMCs (loopback mode test)
SCCs (loopback mode without the time slot assigner)
SCCs (loopback mode with the time slot assigner)
The exception vector table may have been located in ROM, in
which case the PIT vector location should be initialized before
power-on reset.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
Applications
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