MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 508
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Serial Communication Controllers (SCCs)
TC—Tx CRC
CM—Continuous Mode
The following status bits are written by the HDLC controller after it has finished transmitting
the associated data buffer.
UN—Underrun
CT—CTS Lost
Data Length
Tx Data Buffer Pointer
7.10.17.11 HDLC EVENT REGISTER (SCCE). The SCCE is called the HDLC event regis-
ter when the SCC is operating as an HDLC controller. It is a 16-bit register used to report
events recognized by the HDLC channel and to generate interrupts. On recognition of an
event, the HDLC controller will set the corresponding bit in the HDLC event register. Inter-
rupts generated by this register may be masked in the HDLC mask register. An example of
interrupts that may be generated in the HDLC protocol is shown in Figure 7-53.
7-184
This bit is valid only when the L-bit is set; otherwise, it is ignored.
The HDLC controller encountered a transmitter underrun condition while transmitting the
associated data buffer.
CTS in NMSI mode or layer 1 grant was lost in GCI mode during frame transmission. If
data from more than one buffer is currently in the FIFO when this error occurs, this bit will
be set in the Tx BD that is currently open.
The data length is the number of bytes the HDLC controller should transmit from this BD’s
data buffer. It is never modified by the CP. The value of this field should be greater than
zero.
The transmit buffer pointer, which contains the address of the associated data buffer, may
be even or odd. The buffer may reside in either internal or external memory. This value is
never modified by the CP.
0 = Transmit the closing flag after the last data byte. This setting can be used for test-
1 = Transmit the CRC sequence after the last data byte.
0 = Normal operation.
1 = The R-bit is not cleared by the CP after this BD is closed, allowing the associated
ing purposes to send a bad CRC after the data.
data buffer to be retransmitted automatically when the CP next accesses this BD.
However, the R-bit will be cleared if an error occurs during transmission, regard-
less of the CM bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
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