MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 792
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
MC68360VR25VL
Manufacturer:
Exar
Quantity:
160
Company:
Part Number:
MC68360VR25VL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Part Number:
MC68360VR25VLR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Applications
9.7.4 Test Pattern Generation
The easiest way to generate the test pattern is to use the QUICC CPU32+ to transfer the
test pattern over its I/O pins using a bit-banging technique.
The test pattern output data is written to the I/O ports, and therefore to the pins, by writing
to the digital output ports (MTCK, MTMS, and MTDI); the result is read back by simply read-
ing the MTDO pin. A data area is created in memory to hold the test pattern. The CPU32+
compares the result on the MTDO pin to the respective expected result in memory.
Figure 9-26 shows an example of the pattern that would be stored in the memory array. The
three leftmost columns are output signals written to the I/O port, and the right column is the
result expected to be read back. Since the clock signal is part of the pattern and not sepa-
rately generated, both clock phases are represented, and thus two entries comprise each
TCK clock cycle.
9-72
TDO
TMS
TCK
TDI
MUX:
IF MM = 1 THEN B
IF MM = 0 THEN A
FROM LAST DEVICE IN SCAN LOOP
A
B
MUX
EN
OUT
Figure 9-25. Signal Routing for Test Bus Master
TO FIRST DEVICE IN SCAN LOOP
Freescale Semiconductor, Inc.
For More Information On This Product,
A
B
MUX
EN
OUT
MC68360 USER’S MANUAL
Go to: www.freescale.com
A
B
MUX
EN
OUT
EN
IN TEST MASTER MODE
I/O FUNCTIONS IF NOT
LATCH
MTDI
MTMS
MTCK
MTDO
MM
QUICC WITHOUT
TAP IN USE
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