MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 547
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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7.10.21.4 ACHIEVING SYNCHRONIZATION IN TRANSPARENT MODE. Once the SCC
transmitter is enabled for transparent operation in the GSMR, the Tx BD is prepared for the
SCC, and the transmit FIFO has been preloaded by the SDMA channel, one additional pro-
cess must occur before data can be transmitted—i.e., transmit synchronization.
Similarly, once the SCC receiver is enabled for transparent operation in the GSMR and the
Rx BD is made empty for the SCC, one additional process must occur before data can be
received—receive synchronization.
The synchronization process gives the user bit-level control over when the transmission and
reception can begin. There are two basic methods: an in-line synchronization pattern and
external synchronization signals.
7.10.21.4.1 In-Line Synchronization Pattern. The transparent channel can be pro-
grammed to transmit and receive a synchronization pattern if the SYNL bits in the GSMR
are non-zero. The pattern is defined in the DSR. The length of the SYNC pattern is defined
in the SYNL bits in the GSMR.
The receiver synchronizes on the synchronization pattern that is located in the DSR. For
instance, if a 4-bit SYNC is selected, then reception begins as soon as these four bits are
received, beginning with the first bit following the 4-bit SYNC.
The transmitter can synchronize on the receiver pattern if the RSYN bit in the GSMR is set.
This effectively links the transmitter synchronization to the receiver synchronization.
External Synchronization Signals
If the SYNL bits in the GSMR are programmed to 00, an external signal is used to begin the
sequence. The CTS pin is used for the transmitter, and the CD pin is used for the receiver.
The CD and CTS pins share two options: the pulse option and the sampling option.
The pulse option determines whether the CD pin or CTS pins need only be asserted once
to begin reception/transmission or whether the CD pin or CTS pins must be asserted and
stay asserted for the duration of the transparent frame. This is controlled by the CDP and
CTSP bits in the GSMR. If the user expects a continuous stream of data without interruption,
then the pulse operation should be used. However, if the user is trying to identify frames of
transparent data, then the envelope mode of the CD and CTS pins should be used.
15
15
15
14
14
14
4-BIT SYNC
13
13
13
The MC68302 transparent mode offered the EXSYN bit, which,
when set, gave the pulse behavior.
12
12
12
8-BIT SYNC
Freescale Semiconductor, Inc.
11
11
11
For More Information On This Product,
10
10
10
MC68360 USER’S MANUAL
Go to: www.freescale.com
9
9
9
16-BIT SYNC
NOTE
8
8
8
7
7
7
Serial Communication Controllers (SCCs)
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
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