CorePCI Eval Board MICROSEMI, CorePCI Eval Board Datasheet - Page 11

• Manufacturer Part Number: CorePCI Eval Board
• Description: MCU, MPU & DSP Development Tools CorePCI v5.41
• Manufacturer: MICROSEMI

Specifications of CorePCI Eval Board

• Processor To Be Evaluated: SX-A device
• Interface Type: RS-232

Table 6 • CorePCI Backend Interface Signal (Continued)
Name
BUSY
EXT_INTn
CS_CONTROLn
RD_CONTROLn
WR_CONTROLn
CONTROL_ADD[1:0] Input
MASTER_BE[3:0]
MASTER_BE64[3:0]
Notes:
1. Active LOW signals are designated with a trailing lower-case n.
2. Signals ending in "CYC" become valid as the same cycle DP_START is active and will remain valid throughout the current cycle (until
3. MADDR_WIDTH is defined in
4. All inputs should be synchronous to the PCI clock.
DP_DONE is asserted).
1,2
Type
Input
Input
Input
Input
Input
Input
Input
Table 22 on page
Description
Active high signal indicating that the backend controller cannot complete the current transfer.
When BUSY is active at the beginning of a transfer, the Target controller will perform a retry
cycle. If BUSY is activated after some data has been transferred, the Target controller will
perform a disconnect cycle, either with or without data. The signal affects the Target function
only, it is ignored during master operations.
Active low interrupt from the backend. When PCI interrupts are enabled, this should cause an
INTAn signal to be asserted.
Active low chip select to the DMA registers (Master and Target+Master functions).
Active low synchronous read enable for the DMA registers (Master and Target+Master
functions only).
Active low synchronous write enable for the DMA registers (Master and Target+Master
functions only).
Two-bit address used to address the DMA registers from the backend (Master and
Target+Master functions only).
Active low-byte enable inputs used during master transfer to drive the lower CBE lines.
Active low-byte enable inputs used during master transfer to drive the upper CBE lines
20.
v4.0
CorePCI v5.41
11