CorePCI Eval Board MICROSEMI, CorePCI Eval Board Datasheet - Page 18

• Manufacturer Part Number: CorePCI Eval Board
• Description: MCU, MPU & DSP Development Tools CorePCI v5.41
• Manufacturer: MICROSEMI

Specifications of CorePCI Eval Board

• Processor To Be Evaluated: SX-A device
• Interface Type: RS-232

Table 20 • DMA Control Register
1 8
Bit
0–1
2
3
4
5
6
7
8
9
10
15–14
13–11
27–16
CorePCI v5.41
Type
RW
RO
RW
RW
RW
RW
RW
RW
RW
RW
RO
RW
RW*
Description
DMA Error
00 – No Error
01 – Master Abort
10 – Parity Error
11 – Target Abort
DMA Done
A '1' indicates that the DMA transfer is done. Writing a '0' clears this bit.
DMA Direction
A '1' indicates a read from PCI and a write to RAM. A '0' indicates a read from RAM and a write to
PCI.
DMA Request
Writing a '1' will initiate a DMA transfer and the bit will remain set until the DMA transfer
completes or an error occurs (Master abort or Target abort).
DMA Enable
This bit must be set to '1' to enable any DMA transfers.
DMA Interrupt Status
A '1' in this bit indicates the DMA cycle has completed and the interrupt is active. The user clears
this bit by writing a '1' to this bit. Set to '0' after reset.
DMA Interrupt Enable
Writing a '1' to this bit enables the DMA complete interrupt. Set to '0' after reset.
External Interrupt Status
A '1' in this bit indicates an active external interrupt condition (assertion of EXT_INTn). The user
clears it by writing a '1' to this bit position. Set to '0' after reset.
External Interrupt Enable
Writing a '1' to this bit enables the external interrupt signal. Writing a '0' to this bit disables
external interrupt support.
Memory Transfer Width
Writing a '1' to this bit enables a 64-bit memory transaction. For 32-bit CorePCI cores, this bit is
read-only and is set to a '0'.
Reserved (set to '00'b).
Sets the type of PCI cycle performed:
000 – Memory Cycle
001 – Configuration Cycle
010 – Interrupt Acknowledge
100 – I/O Cycle
Other encodings should not be used.
DMA Transfer Length
Number of bytes to be transferred. Bits 16 and 17 are set to '0' since DMA transactions must be on
DWORD boundaries. During a DMA transfer, this location will decrement indicating the number of
bytes remaining. To transfer 1024 DWORDs, this location should be set to all zeros.
v4.0