CorePCI Eval Board MICROSEMI, CorePCI Eval Board Datasheet - Page 14

• Manufacturer Part Number: CorePCI Eval Board
• Description: MCU, MPU & DSP Development Tools CorePCI v5.41
• Manufacturer: MICROSEMI

Specifications of CorePCI Eval Board

• Processor To Be Evaluated: SX-A device
• Interface Type: RS-232

Table 9 • Command Register (04h)
Table 10 • Status Register (06h)
1 4
Bit
0
1
2
3
4
5
6
7
8
9
10
15–11
Note: RW = Read and write
Bit
2–0
3
4
5
Note: The RW capability in the status register is restricted to clearing the bit by writing a '1' into the bit location.
CorePCI v5.41
RO = Read only
Type
RW
RW
RW
RO
RO
RO
RW
RO
RW
RO
RO
Type
RO
RO
RO
RW
RO
Description
I/O Space
A value of '0' disables the device’s response to I/O space addresses. Set to '0' after reset.
Memory Space
A value of '0' disables the device’s response to memory space addresses. Set to '0' after reset.
Bus Master
When set to a '1' this bit enables the macro to behave as a PCI bus Master. For Target-only
implementation, this bit is read-only and is set to '0'.
Special Cycles
No response to special cycles. It is set to '0'.
Memory write and invalidate enable
Memory write and invalidate not supported. It is set to '0'.
VGA Palette Snoop
Assumes non-VGA peripheral. It is set to '0'.
Parity Error Response
When '0' the device ignores parity errors. When '1' normal parity checking is performed. Set to '0'
after reset.
Wait Cycle Control
No data-stepping supported. It is set to '0'.
SERRn Enable
When '0' the SERRn driver is disabled. It is set to '0' after reset.
Fast Back-to-Back Enable
Set to
Interrupt Disable
When set this prevents the Core from asserting its INTAn output. This bit is set to '0' after reset.
Reserved and set to all
Description
Reserved—set to
Interrupt Status
This bit reflects the status of the INTAn output.
Capabilities List
When the HOT_SWAP_EN customization constant is set to a '1', the bit is set to a '1'; otherwise, it
is set to '0'.
66 MHz Capable
Should be set to '1' to indicate a 66 MHz Target, or '0' to indicate a 33 MHz Target. The value
depends on the MHZ_66 customization constant.
'
0
'
. Only fast back-to-back transactions to same agent are allowed.
'
000
'
b.
'
0
'
s.
v4.0