CorePCI Eval Board MICROSEMI, CorePCI Eval Board Datasheet - Page 8

• Manufacturer Part Number: CorePCI Eval Board
• Description: MCU, MPU & DSP Development Tools CorePCI v5.41
• Manufacturer: MICROSEMI

Specifications of CorePCI Eval Board

• Processor To Be Evaluated: SX-A device
• Interface Type: RS-232

Table 5 • CorePCI Interface Signals
8
Name
CLK
RSTn
AD
CBE
PAR
PAR64
FRAMEn
REQ64n
IRDYn
TRDYn
STOPn
IDSEL
DEVSELn
ACK64n
REQn
GNTn
PERRn
SERRn
INTAn
Note: *Active LOW signals are designated with a trailing lower-case n.
CorePCI v5.41
*
Type
Input
Input
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional (STS) Active LOW signal indicating the beginning and duration of an access. While FRAMEn is asserted,
Bidirectional (STS) Active LOW signal with the same timing as FRAMEn indicating that the Master requests a data
Bidirectional (STS) Active LOW signal indicating that the bus Master is ready to complete the current dataphase
Bidirectional (STS) Active LOW signal indicating that the Target is ready to complete the current dataphase
Bidirectional (STS) Active LOW signal from the Target requesting termination of the current transaction.
Input
Bidirectional (STS) Active LOW output from the Target indicating that it is the Target of the current access.
Bidirectional (STS) Active LOW output from the Target indicating that it is capable of transferring data on the full
Output
Input
Bidirectional (STS) Active LOW parity error signal
Open Drain
Open Drain
Description
33 MHz or 66 MHz clock input for the PCI core
Active LOW asynchronous reset
Multiplexed 32-bit or 64-bit address and data bus. Valid address is indicated by FRAMEn
assertion.
Bus command and byte enable information. During the address phase, the lower 4 bits define
the bus command. During the dataphase, they define the byte enables. This bus is 4 bits for 32-
bit PCI systems and 8 bits in 64-bit systems.
Parity signal. Parity is even across AD[31:0] and CBE[3:0].
Upper parity signal. Parity is even across AD[63:32] and CBE[7:4]. This signal is not required for
32-bit PCI systems.
data transfers continue.
transfer over the full 64-bit bus. This signal is not required for 32-bit PCI systems.
transaction.
transaction.
Active HIGH Target select used during configuration read and write transactions.
64-bit PCI bus. This signal is driven in response to the REQ64n signal and has the same timing as
DEVSELn. This signal is not required in 32-bit PCI systems.
Active LOW output used to request bus ownership. This signal is asserted by the PCI Master
controller whenever Master/DMA mode is enabled.
Active LOW input from the system arbiter indicating that the core may claim bus ownership.
Active LOW system error signal. This signal reports PCI address parity errors.
Active LOW interrupt request
v4.0