CorePCI Eval Board MICROSEMI, CorePCI Eval Board Datasheet - Page 19

• Manufacturer Part Number: CorePCI Eval Board
• Description: MCU, MPU & DSP Development Tools CorePCI v5.41
• Manufacturer: MICROSEMI

Specifications of CorePCI Eval Board

• Processor To Be Evaluated: SX-A device
• Interface Type: RS-232

Table 20 • DMA Control Register (Continued)
Master Register Access
There are three different ways that the Master registers
can be accessed. The address locations for the DMA
registers are listed in
registers are only accessible from the PCI bus and can be
either I/O mapped or configuration mapped. For the I/O
mapping, the core uses Base Address Register #2 to
assign a 256-byte memory space. The registers are then
located at addresses 40h, 44h, and 48h. To map these
registers into I/O, the DMA_IN_IO customization constant
Table 21 • Address Locations for the DMA Registers
Customization Options
CorePCI has a variety of options for user customization. A
special package defining a list of variables that allow the
user to optimize the core for a particular application is
included with the source design files. All of the constants
are applicable to the Target+DMA function. For
Target+Master functions, the DMA_IN_IO constant is not
required. For Target functions, the DMA_IN_IO and
DMA_CNT_EN constants are not required. For Master
functions, only the BIT64 and the MADDR_WIDTH
constants are used.
descriptions.
Configuration Register Constants
To set the read-only registers in the configuration space,
a variety of constants are defined. The constants support
the definitions of the device ID register, vendor ID
register, class code registers, revision ID register,
subsystem ID, and the subsystem vendor ID.
Bit
28
31–29
Register Name
PCI Address
Ram Address
DMA Control Register
Type
RO
RW
Table 22
Table
21. For master functions, the
lists the variables and their
Description
Reserved (set to '0').
Maximum Burst Length
When set to '000'b, the Master controller will attempt to complete the requested transfer in a
single burst. When set to non-zero, the Master will automatically break up long bursts and limit
burst transfer lengths to 2**(n-1) where n is the decimal value of bits 31:29. Therefore, maximum
transfer lengths can be limited to 1, 2, 4, 8, 16, 32 or 64 dataphases. For example, if the maximum
burst length is set to '101'b (16 transfers), then a 1024 DWORD transfer count would be broken
up into 64 individual PCI accesses.
Configuration Address
40h
44h
48h
v4.0
must be set to a '1'. When this constant is set to a '0', the
registers are configuration mapped again at locations
40h, 44h, and 48h.
For Master and Target+Master functions, these registers
are accessed via the backend. A two-bit address bus,
CONTROL_ADD[1:0], is provided along with chip select,
read, and write signals.
Other Options
In addition to the read-only configuration definitions,
CorePCI offers a variety of customization options
summarized as follows:
• 32-bit or 64-bit data size (BIT64)
• 33 or 66 MHz operation (MHZ_66)
• BAR0 address size (MADDR_WIDTH)
• Optional
• Option to have the DMA registers mapped into I/O
BAR1_IO_MEMORY,
BAR1_PREFETCH
space (DMA_IN_IO) for Target+DMA functions
I/O Address
40h
44h
48h
BAR1
definitions
BAR1_ADDR_WIDTH,
Backend Address
00b
01b
10b
(BAR1_ENABLE,
CorePCI v5.41
and
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