CorePCI Eval Board MICROSEMI, CorePCI Eval Board Datasheet - Page 15

• Manufacturer Part Number: CorePCI Eval Board
• Description: MCU, MPU & DSP Development Tools CorePCI v5.41
• Manufacturer: MICROSEMI

Specifications of CorePCI Eval Board

• Processor To Be Evaluated: SX-A device
• Interface Type: RS-232

Table 10 • Status Register (06h) (Continued)
Bit
6
7
8
10–9
11
12
13
14
15
Note: The RW capability in the status register is restricted to clearing the bit by writing a '1' into the bit location.
Type
RO
RO
RW
RO
RW
RW
RW
RW
RW
Description
UDF Supported
Set to '0' – no user definable features.
Fast Back-to-Back Capable
Set to '0' – fast back-to-back to same agent only.
Data Parity Error Detected
If the Master controller detects a PERRn, this bit is set to a '1'. This bit is read-only in Target-only
implementations and is set to '0'.
DEVSELn Timing
Set to '10' – slow DEVSELn response.
Signaled Target Abort
Set to '0' at system reset. This bit is set to a '1' by internal logic whenever a Target abort cycle is
executed.
Received Target Abort
If the Master controller detects a Target Abort, this bit is set to a '1'. This bit is read-only in Target-
only implementations and is set to '0'.
Received Master Abort
If the Master controller performs a Master Abort, this bit is set to a '1'. This bit is read-only in
Target-only implementations and is set to '0'.
Signaled System Error
Set to '0' at system reset. This bit is set to '1' by internal logic whenever the SERRn signal is
asserted by the Target.
Detected Parity Error
Set to '0' at system reset. This bit is set to '1' by internal logic whenever a parity error, address, or
data is detected, regardless of the value of bit 6 in the command register.
v4.0
CorePCI v5.41
15