CorePCI Eval Board MICROSEMI, CorePCI Eval Board Datasheet - Page 27

• Manufacturer Part Number: CorePCI Eval Board
• Description: MCU, MPU & DSP Development Tools CorePCI v5.41
• Manufacturer: MICROSEMI

Specifications of CorePCI Eval Board

• Processor To Be Evaluated: SX-A device
• Interface Type: RS-232

Notes:
1. When FRAMEn and REQ64n is asserted and the command bus is '0110', then a 64-bit read from memory space is indicated.
2. The Target will compare the address to the programmed space set in the memory base address register.
3. If an address hit occurs, then the Target asserts DP_START and DP_START64 in cycle 3 and claims the PCI bus by asserting DEVSELn
4. Data transfer from the backend begins on the rising edge of cycle 7 and continues for each subsequent cycle until the PCI bus ends
5. For 64-bit transfers, the MEM_ADDRESS will increment by 2 each cycle.
6. The PCI transaction completes when TRDYn is de-asserted in cycle 10.
7. For this case, the PIPE_FULL_CNT is set to '000' (See
See
Figure 10 • 64-bit Burst Read with Zero Wait States
and ACK64n in cycle 4.
the data transfer. The backend prefetches three DWORDs during zero-wait- state bursts.
"Backend Latency Control" on page 31
MEM_DATA[63:32]
MEM_DATA[31:0]
MEM_ADDRESS
RD_BE_NOW64
RD_BE_NOW
DP_START64
RD_BE_RDY
DP_START
AD[63:32]
DP_DONE
DEVSELn
AD[31:0]
FRAMEn
ACK64n
REQ64n
TRDYn
PAR64
STOPn
IRDYn
PAR
CLK
CBE
1
for RD_CYC and BARn_CYC timing.
addr
0110
zero
2
Paddr
zero
3
"Backend Latency Control" on page 31
4
v4.0
5
add0
data1
data0
byte enables
6
data0
data1
data3
data2
add2
7
data2
data3
data5
data4
add4
Pd0
Pd1
8
data4
data5
data7
data6
add6
Pd2
Pd3
9
for more information).
data6
data7
data9
data8
add8
Pd4
Pd5
10
dataB
dataA
addA
Pd6
Pd7
11
12
CorePCI v5.41
27