CorePCI Eval Board MICROSEMI, CorePCI Eval Board Datasheet - Page 30

• Manufacturer Part Number: CorePCI Eval Board
• Description: MCU, MPU & DSP Development Tools CorePCI v5.41
• Manufacturer: MICROSEMI

Specifications of CorePCI Eval Board

• Processor To Be Evaluated: SX-A device
• Interface Type: RS-232

Notes:
1. In the example, the flow of data is interrupted from the PCI Master de-assertion of IRDYn in cycle 3. The PCI Master inserts two wait
2. The backend can also interrupt the flow of data by de-asserting the WR_BE_RDY signal. One cycle later, TRDYn is de-asserted, halting
Figure 13 • PCI Write Illustrating both IRDYn and TRDYn De-Assertion
3 0
MEM_ADDRESS[23:2]
CorePCI v5.41
states. This state of the PCI bus is defined to the backend by de-asserting the WR_BE_NOW[3:0] bus one cycle later.
the flow of data on the PCI bus. The backend must accept two DWORDs of data following de-assertion of the WR_BE_RDY signal.
MEM_DATA[31:0]
WR_BE_NOW
WR_BE_RDY
DP_START
DP_DONE
AD[31:0]
DEVSELn
FRAMEn
CBE[3:0]
TRDYn
STOPn
IRDYn
PAR
CLK
data2
data1
add1
Pd1
1
data3
data2
add2
Pd2
2
data4
data3
add3
Pd3
3
data4
add4
Pd4
4
5
data5
add5
6
v4.0
data6
data5
Pd5
7
data7
data6
add6
Pd6
byte enables
8
data8
data7
add7
Pd7
9
data9
data8
add8
Pd8
10
data9
add9
Pd9
11
12
data10
13
data10
add10
Pd10
14
data11
15
data12
data11
add11
Pd11
16