CorePCI Eval Board MICROSEMI, CorePCI Eval Board Datasheet - Page 33

• Manufacturer Part Number: CorePCI Eval Board
• Description: MCU, MPU & DSP Development Tools CorePCI v5.41
• Manufacturer: MICROSEMI

Specifications of CorePCI Eval Board

• Processor To Be Evaluated: SX-A device
• Interface Type: RS-232

Target Retry and Disconnect
When the backend is busy or unable to provide the data
requested, the Target controller will respond with either
a retry or a disconnect cycle. If the backend has
arbitrated for control of the backend bus and the
BE_GNT signal is active, then the controller will respond
with a retry cycle
is unable to respond by asserting STOPn and DEVSELn
simultaneously.
Notes:
1. If BE_GNT or BUSY are asserted at the beginning of a cycle, then a retry is initiated.
2. The Target simultaneously asserts the STOPn and DEVSELn signals without asserting the TRDYn signal.
3. The Master will begin cycle termination by de-asserting FRAMEn first and then IRDYn on a subsequent cycle.
Figure 17 • Target Retry
(Figure
17). The Target indicates that it
DEVSELn
AD[31:0]
FRAMEn
CBE[3:0]
BE_GNT
TRDYn
STOPn
IRDYn
PAR
CLK
1
0110
addr
2
Paddr
3
v4.0
byte enables
During a regular PCI transfer, the RD_BE_RDY and
WR_BE_RDY indicate that data is available to be received
from or transmitted to the backend. If, during a PCI
cycle, the backend becomes unable to read or write data,
then the *_RD_RDY signals are de-asserted. After several
cycles, a PCI time-out will occur and the Target controller
will initiate a Target disconnect without data cycle
(Figure 18 on page
4
5
6
7
34).
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CorePCI v5.41
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