CorePCI Eval Board MICROSEMI, CorePCI Eval Board Datasheet - Page 32

• Manufacturer Part Number: CorePCI Eval Board
• Description: MCU, MPU & DSP Development Tools CorePCI v5.41
• Manufacturer: MICROSEMI

Specifications of CorePCI Eval Board

• Processor To Be Evaluated: SX-A device
• Interface Type: RS-232

Figure 15 • Backend Latency Read Transaction
Target Abort
The backend may cause a target abort
abort, which is defined by the Target simultaneously asserting the STOPn signal and de-asserting the DEVSELn signal.
Notes:
1. During a PCI cycle, the backend ERROR signal indicates that a problem occurred on the backend such that the transfer cannot be
2. The Target initiates a Target abort by asserting STOPn and de-asserting DEVSELn in the same cycle.
3. The Master will begin cycle termination by de-asserting FRAMEn first, and then IRDYn on a subsequent cycle.
4. The transaction completes when STOPn is de-asserted in cycle 9.
5. The *_BE_RDY signal should be de-asserted whenever the ERROR signal is asserted.
Figure 16 • Target Abort Cycle
3 2
CorePCI v5.41
completed.
MEM_ADDRESS
PIPE_FULL_CNT
RD_BE_NOW
MEM_DATA
RD_BE_RDY
DP_START
DP_DONE
DEVSELn
FRAMEn
DEVSELn
AD[31:0]
FRAMEn
TRDYn
CBE[3:0]
STOPn
IRDYn
TRDYn
ERROR
STOPn
IRDYn
PAR
CBE
CLK
AD
PAR
CLK
1
1
0110
addr
addr
0111
2
000
(Figure
2
Paddr
Paddr
3
16) by asserting the ERROR input. The ERROR input will cause a Target
3
4
data0
4
5
add0
v4.0
byte enables
Pdata0
5
byte enables
6
data0
add1
6
7
data1
data0
data1
add2
7
8
001
data2
Pd1
data1
data2
add3
Pd0
8
9
data3
Pd2
data2
data3
add4
Pd1
9
10
Pd3
data4
add5
Pd2
10
11
data5
add6
11
12
12