CorePCI Eval Board MICROSEMI, CorePCI Eval Board Datasheet - Page 37

• Manufacturer Part Number: CorePCI Eval Board
• Description: MCU, MPU & DSP Development Tools CorePCI v5.41
• Manufacturer: MICROSEMI

Specifications of CorePCI Eval Board

• Processor To Be Evaluated: SX-A device
• Interface Type: RS-232

Notes:
1. Once CorePCI is granted the PCI bus, the core asserts DP_START and begins the process of enabling the bus to drive FRAMEn.
2. The PCI address and command are valid at the same time that FRAMEn is driven low.
3. Once FRAMEn is driven, if the backend is prepared to supply data, then IRDYn is asserted on the following cycle. The core can store
4. The core then waits for the Target to complete the transfer by asserting TRDYn.
5. The transfer continues until either the transfer count is exhausted or the Target disconnects.
6. Cycle termination is initiated by driving FRAMEn high.
7. The number of clock cycles from DP_START to FRAMEn assertion can be increased by asserting STALL_MASTER.
Figure 22 • Zero-Wait-State DMA Master Write (Write to the PCI Bus)
MEM_ADDRESS[23:2]
up to two DWORDs of data. If the Target has not responded with a TRDYn when the second DWORD is read, then the core will cease
reading as indicated by the RD_BE_NOW signal de-asserting.
MEM_DATA[31:0]
RD_BE_NOW
RD_BE_RDY
BARn_CYC
DP_START
DP_DONE
C_BE[3:0]
DEVSELn
AD[31:0]
FRAMEn
RD_CYC
TRDYn
STOPn
IRDYn
PAR
CLK
1
2
3
4
5
6
add0
v4.0
7
data0
CMD
addr
8
data1
Paddr
add1
9
data0
10
data2
add2
Pd0
byte enables
11
data1
12
addr3
data3
data2
Pd1
13
addr4
data4
data3
Pd2
14
CorePCI v5.41
addr5
data5
Pd3
15
addr6
16
37