CorePCI Eval Board MICROSEMI, CorePCI Eval Board Datasheet - Page 2

• Manufacturer Part Number: CorePCI Eval Board
• Description: MCU, MPU & DSP Development Tools CorePCI v5.41
• Manufacturer: MICROSEMI

Specifications of CorePCI Eval Board

• Processor To Be Evaluated: SX-A device
• Interface Type: RS-232

General Description
CorePCI connects I/O, memory, and processor subsystem
resources to the main system via the PCI bus. CorePCI is
intended for use with a wide variety of peripherals
where high-performance data transactions are required.
Figure 1 on page 2
using the baseline IP core. While CorePCI can handle any
transfer rate, most applications will operate at zero wait
states. When required, wait states can automatically be
inserted by a slower peripheral.
The core consists of up to four basic units: the Target
controller, the Master controller, the backend, and the
Figure 1 • CorePCI System Block Diagram
2
CorePCI v5.41
depicts typical system applications
IRDYn
STOPn
DEVSELn
ACK64n
TRDYn
SERRn
PAR64
PERRn
GNTn
RSTn
IDSEL
AD
PAR
CBE
INTAn
CLK
FRAMEn
REQ64n
REQn
PCI Bus
Master
Target+Master
Controller
CorePCI
Memory Control Signals
MEM_ADDRESS BUS
MEM_DATA BUS
Master Control Signals
Bridge
v4.0
BAR1_ENABLE
wrapper. Both the Target and Master controllers remain
constant for a variety of backends. A backend controller
provides the necessary control for the I/O or memory
subsystem and interfaces to the Target controller
through a generic interface. The wrapper combines the
Target and Master blocks with the backend for
implementation in a single Actel device.
CorePCI can be customized in two different ways. First, a
variety of variables are provided to easily change
parameters such as memory and I/O sizes. The second
method is to develop user-specific backend controllers
for non-standard peripherals.
Target
Memory or I/O
Sync SRAM
Sync DRAM
System CPU
Subsystem
Subsystem
Optional
Memory