PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 21

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
2.6.1 PREFETCHABLE READ TRANSACTIONS
2.6.2 DYNAMIC PREFETCHING CONTROL
2.6.3 NON-PREFETCHABLE READ TRANSACTIONS
A prefetchable read transaction is a read transaction where the bridge performs speculative DWORD
reads, transferring data from the target before it is requested from the initiator. This behavior allows a
prefetchable read transaction to consist of multiple data transfers. However, byte enable bits cannot be
forwarded for all data phases as is done for the single data phase of the non-prefetchable read
transaction. For prefetchable read transactions, the bridge forces all byte enable bits to be turned on for
all data phases.
Prefetchable behavior is used for memory read line and memory read multiple transactions, as well as
for memory read transactions that fall into prefetchable memory space.
The amount of data that is pre-fetched depends on the type of transaction. The amount of pre-fetching
may also be affected by the amount of free buffer space available in the bridge, and by any read address
boundaries encountered.
Pre-fetching should not be used for those read transactions that have side effects in the target device,
that is, control and status registers, FIFO’s, and so on. The target device’s base address register or
registers indicate if a memory address region is prefetchable.
For prefetchable reads described in the previous section, the prefetching length is normally predefined
and cannot be changed once it is set. This may cause some inefficiency as the prefetching length
determined could be larger or smaller than the actual data being prefetched. To make prefetching more
efficient, PI7C8140A incorporates dynamic prefetching control logic. This logic regulates the different
PCI memory read commands (MR – memory read, MRL – memory read line, and MRM – memory
read multiple) to improve memory read burst performance. The bridge tracks every memory read burst
transaction and tallies the status. By using the status information, the bridge can determine to increase,
reduce, or keep the same cache line length to be prefetched. Over time, the bridge can better match the
correct cache line setting to the length of data being requested. The dynamic prefetching control logic is
set with bits[3:2] offset 48h.
A non-prefetchable read transaction is a read transaction where the bridge requests one and only one
DWORD from the target and disconnects the initiator after delivery of the first DWORD of read data.
Unlike prefetchable read transactions, the bridge forwards the read byte enable information for the data
phase.
Non-prefetchable behavior is used for I/O and configuration read transactions, as well as for memory
read transactions that fall into non-prefetchable memory space.
If extra read transactions could have side effects, for example, when accessing a FIFO, use non-
prefetchable read transactions to those locations. Accordingly, if it is important to retain the value of the
byte enable bits during the data phase, use non-prefetchable read transactions. If these locations are
mapped in memory space, use the memory read command and map the target into non-prefetchable
(memory-mapped I/O) memory space to use non-prefetching behavior.
Page 21 of 82
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
PI7C8140A