PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 66

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
13.2.22 PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER
13.2.23 I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h
13.2.24 I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h
13.2.25 CAPABILITY POINTER REGISTER – OFFSET 34h
13.2.26 INTERRUPT LINE REGISTER – OFFSET 3Ch
13.2.27 INTERRUPT PIN REGISTER – OFFSET 3Ch
– OFFSET 2Ch
Bit
31:0
Bit
15:0
Bit
31:16
Bit
7:0
Bit
7:0
Bit
15:8
Function
Prefetchable
Memory Limit
Address, Upper
32-bits [63:32]
Function
I/O Base
Address, Upper
16-bits [31:16]
Function
I/O Limit
Address, Upper
16-bits [31:16]
Function
Capability
Pointer
Function
Interrupt Line
Function
Interrupt Pin
Type
RW
Type
RW
Type
RW
Type
RO
Type
RW
Type
RO
Description
Defines the upper 32-bits of a 64-bit top address of an address range for the
bridge to determine when to forward memory read and write transactions from
one interface to the other.
Reset to 0
Description
Defines the upper 16-bits of a 32-bit bottom address of an address range for the
bridge to determine when to forward I/O transactions from one interface to the
other.
Reset to 0
Description
Defines the upper 16-bits of a 32-bit top address of an address range for the
bridge to determine when to forward I/O transactions from one interface to the
other.
Reset to 0
Description
Pointer points to the PCI power management registers (80h).
Reset to 80h
Description
Bridge does not implement an interrupt signal, so POST programs FFh to this
register.
Description
Bridge does not implement interrupt signal pins.
Reset to 0
Page 66 of 82
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
PI7C8140A