PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 73

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
13.2.37 P_SERR# STATUS REGISTER – OFFSET 68h
Bit
5:4
7:6
8
13:9
15:14
Bit
16
17
18
19
20
21
22
23
Function
Clock 2 disable
Clock 3 disable
Reserved
Reserved
Reserved
Function
Address Parity
Error
Posted Write
Data Parity
Error
Posted Write
Non-delivery
Target Abort
during Posted
Write
Master Abort
during Posted
Write
Delayed Write
Non-delivery
Delayed Read –
No Data from
Target
Delayed
Transaction
Master Timeout
Type
RW
RW
RO
RO
RO
Type
RWC
RWC
RWC
RWC
RWC
RWC
RWC
RWC
Description
S_CLKOUT[2] (slot 2) Enable
00: enable S_CLKOUT[2]
01: enable S_CLKOUT[2]
10: enable S_CLKOUT[2]
11: disable S_CLKOUT[2] and driven LOW
Reset to 00
S_CLKOUT[3] (slot 3) Enable
00: enable S_CLKOUT[3]
01: enable S_CLKOUT[3]
10: enable S_CLKOUT[3]
11: disable S_CLKOUT[3] and driven LOW
Reset to 00
Reserved. Reset to 0
Reserved. Reset to 1Fh
Reserved. Reset to 00
Description
1: Signal P_SERR# was asserted because an address parity error was detected on
P or S bus.
Reset to 0
1: Signal P_SERR# was asserted because a posted write data parity error was
detected on the target bus.
Reset to 0
1: Signal P_SERR# was asserted because the bridge was unable to deliver post
memory write data to the target after 2
Reset to 0
1: Signal P_SERR# was asserted because the bridge received a target abort when
delivering post memory write data.
Reset to 0.
1: Signal P_SERR# was asserted because the bridge received a master abort when
attempting to deliver post memory write data
Reset to 0.
1: Signal P_SERR# was asserted because the bridge was unable to deliver
delayed write data after 2
Reset to 0
1: Signal P_SERR# was asserted because the bridge was unable to read any data
from the target after 2
Reset to 0.
1: Signal P_SERR# was asserted because a master did not repeat a read or write
transaction before master timeout.
Reset to 0.
Page 73 of 82
24
attempts.
24
attempts.
24
attempts.
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
PI7C8140A