PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 77
![IC PCI-PCI BRIDGE 2PORT 128-QFP](/photos/16/9/160974/11152007123119_sml.jpg)
PI7C8140AMAE
Manufacturer Part Number
PI7C8140AMAE
Description
IC PCI-PCI BRIDGE 2PORT 128-QFP
Manufacturer
Pericom Semiconductor
Datasheet
1.PI7C8140AMAE.pdf
(82 pages)
Specifications of PI7C8140AMAE
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
128-QFP
Mounting Type
Surface Mount
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3 V to 3.6 V
Supply Current (max)
230 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PI7C8140AMAE
Manufacturer:
Pericom
Quantity:
135
Company:
Part Number:
PI7C8140AMAE
Manufacturer:
SONY
Quantity:
469
Part Number:
PI7C8140AMAE
Manufacturer:
PERICOM
Quantity:
20 000
07-0067
13.2.43 POWER MANAGEMENT DATA REGISTER – OFFSET 84h
13.2.44 PRIMARY MASTER TIMEOUT COUNTER REGISTER – OFFSET 88h
13.2.45 SECONDARY MASTER TIMEOUT COUNTER REGISTER – OFFSET 88h
13.2.46 CAPABILITY ID REGISTER – OFFSET 90h
13.2.47 NEXT ITEM POINTER REGISTER – OFFSET 90h
Bit
1:0
7:2
8
12:9
14:13
15
Bit
15:0
Bit
31:16
Bit
7:0
Bit
15:8
Function
Power State
Reserved
PME# Enable
Data Select
Data Scale
PME status
Function
Primary
Timeout
Function
Secondary
Timeout
Function
Enhanced
Capabilities ID
Function
Next Item
Pointer
Type
RW
RO
RO
RO
RO
RO
Type
RW
Type
RW
Type
RO
Type
RO
Description
Indicates the current power state of the bridge. If an unimplemented power state
is written to this register, the bridge completes the write transaction, ignores the
write data, and does not change the value of the field. Writing a value of D0
when the previous state was D3 cause a chip reset without asserting S_RESET#
00: D0 state
01: D1 state
10: D2 state
11: D3 state
Reset to 0
Read as 0
Read as 0 as the bridge does not support the PME# pin.
Read as 0 as the data register is not implemented.
Read as 0 as the data register is not implemented.
Read as 0 as the PME# pin is not implemented.
Description
Primary timeout occurs after 2
Reset to 8000h.
Description
Secondary timeout occurs after 2
Reset to 8000h.
Description
Read as 06h to indicate that these are power management enhanced capability
registers.
Description
Read as 00h. No other ECP registers.
Page 77 of 82
15
PCI clocks.
15
PCI clocks.
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
PI7C8140A