PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 64

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
13.2.16 SECONDARY STATUS REGISTER – OFFSET 1Ch
13.2.17 MEMORY BASE ADDRESS REGISTER – OFFSET 20h
Bit
15:12
Bit
20:16
21
22
23
24
26:25
27
28
29
30
31
Bit
3:0
Function
I/O Limit
Address
[15:12]
Function
Reserved
66MHz
Capable
Reserved
Fast Back-to-
Back Capable
Data Parity
Error Detected
DEVSEL_L
timing
Signaled Target
Abort
Received
Target Abort
Received
Master Abort
Received
System Error
Detected Parity
Error
Function
Reserved
Type
RW
Type
RO
RO
RO
RO
RWC
RO
RWC
RWC
RWC
RWC
RWC
Type
RO
Description
Defines the top address of the I/O address range for the bridge to determine when
to forward I/O transactions from one interface to the other. The upper 4 bits
correspond to address bits [15:12] and are writable. The lower 12 bits
corresponding to address bits [11:0] are assumed to be FFFh. The upper 16 bits
corresponding to address bits [31:16] are defined in the I/O limit address upper 16
bits address register
Reset to 0
Description
Reset to 0
Set to 1 to indicate bridge is capable of 66MHz operation on the secondary
interface
Reset to 1
Reset to 0
Set to 1 to indicate bridge is capable of decoding fast back-to-back transactions
on the secondary interface to different targets
Reset to 1
Set to 1 when S_PERR# is asserted and bit 6 of command register is set
Reset to 0
DEVSEL# timing (medium decoding)
01: medium DEVSEL# decoding
Reset to 01
Set to 1 (by a target device) whenever a target abort cycle occurs on its secondary
interface
Reset to 0
Set to 1 (by a master device) whenever transactions on its secondary interface are
terminated with target abort
Reset to 0
Set to 1 (by a master) when transactions on its secondary interface are terminated
with Master Abort
Reset to 0
Set to 1 when S_SERR# is asserted
Reset to 0
Set to 1 when address or data parity error is detected on the secondary interface
Reset to 0
Description
Reset to 0
Page 64 of 82
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
PI7C8140A