PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 48

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
Table 5-5 shows assertion of P_PERR#. This signal is set under the following conditions:
Table 5-5. Assertion of P_PERR#
X = don’t care
2
Table 5-6 shows assertion of S_PERR# that is set under the following conditions:
Table 5-6. Assertion of S_PERR#
X = don’t care
2
Table 5-7 shows assertion of P_SERR#. This signal is set under the following conditions:
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
P_PERR#
1 (de-asserted)
1
0 (asserted)
1
0
1
1
1
0
0
1
1
S_PERR#
1 (de-asserted)
0 (asserted)
1
1
1
1
1
0
1
1
0
0
2
2
The bridge is either the target of a write transaction or the initiator of a read transaction on the
primary bus.
The parity-error-response bit must be set in the command register of primary interface.
The bridge detects a data parity error on the primary bus or detects S_PERR# asserted during the
completion phase of a downstream delayed write transaction on the target (secondary) bus.
The bridge is either the target of a write transaction or the initiator of a read transaction on the
secondary bus.
The parity error response bit must be set in the bridge control register of secondary interface.
Bridge detects a data parity error on the secondary bus or detects P_PERR# asserted during the
completion phase of an upstream delayed write transaction on the target (primary) bus.
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Transaction Type
Read
Read
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
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Primary
Primary
Primary
Secondary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Bus Where Error
Bus Where Error
Was Detected
Was Detected
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
x / x
x / x
1 / x
x / x
1 / x
x / x
x / x
x / x
1 / x
1 / 1
x / x
x / x
x / x
x / 1
x / x
x / x
x / x
x / x
x / x
x / 1
x / x
x / x
1 / 1
x / 1
Primary/ Secondary Parity
Primary/ Secondary Parity
Error Response Bits
Error Response Bits
PI7C8140A