PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 65

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
13.2.18 MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h
13.2.19 PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h
13.2.20 PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h
13.2.21 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER
– OFFSET 28h
Bit
15:4
Bit
19:16
31:20
Bit
3:0
15:4
Bit
19:16
31:20
Bit
31:0
Function
Memory Base
Address [15:4]
Function
Reserved
Memory Limit
Address [31:20]
Function
64-bit
addressing
Prefetchable
Memory Base
Address [31:20]
Function
64-bit
addressing
Prefetchable
Memory Limit
Address [31:20]
Function
Prefetchable
Memory Base
Address, Upper
32-bits [63:32]
Type
RW
Type
RO
RW
Type
RO
RW
Type
RO
RW
Type
RW
Description
Defines the bottom address of an address range for the bridge to determine when
to forward memory transactions from one interface to the other. The upper 12
bits correspond to address bits [31:20] and are writable. The lower 20 bits
corresponding to address bits [19:0] are assumed to be 0.
Reset to 0
Description
Reset to 0
Defines the top address of an address range for the bridge to determine when to
forward memory transactions from one interface to the other. The upper 12 bits
correspond to address bits [31:20] and are writable. The lower 20 bits
corresponding to address bits [19:0] are assumed to be FFFFFh.
Description
Indicates 64-bit addressing
0001: 64-bit addressing
Reset to 1
Defines the bottom address of an address range for the bridge to determine when
to forward memory read and write transactions from one interface to the other.
The upper 12 bits correspond to address bits [31:20] and are writable. The lower
20 bits are assumed to be 0. The memory base register upper 32 bits contains the
upper half of the base address.
Description
Indicates 64-bit addressing
0001: 64-bit addressing
Reset to 1
Defines the top address of an address range for the bridge to determine when to
forward memory read and write transactions from one interface to the other. The
upper 12 bits correspond to address bits [31:20] and are writable. The lower 20
bits are assumed to be FFFFFh. The memory limit upper 32 bits register contains
the upper half of the limit address.
Description
Defines the upper 32-bits of a 64-bit bottom address of an address range for the
bridge to determine when to forward memory read and write transactions from
one interface to the other.
Reset to 0
Page 65 of 82
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
PI7C8140A