M29F400FB55M3F2 Micron Technology Inc, M29F400FB55M3F2 Datasheet - Page 20

• Manufacturer Part Number: M29F400FB55M3F2
• Manufacturer: Micron Technology Inc

Specifications of M29F400FB55M3F2

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 55ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 19/18Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 125C
• Package Type: SO W
• Program/erase Volt (typ): 4.5 to 5.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Automotive
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 512K/256K
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Compliant

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Signal Descriptions
See
connected to this device.
Address Inputs (A0-A19)
The Address Inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
Interface of the Program/Erase Controller.
Data Inputs/Outputs (DQ0-DQ7)
The Data Inputs/Outputs output the data stored at the selected address during a Bus Read
operation. During Bus Write operations they represent the commands sent to the Command
Interface of the Program/Erase Controller.
Data Inputs/Outputs (DQ8-DQ14)
The Data Inputs/Outputs output the data stored at the selected address during a Bus Read
operation when BYTE is High, V
high impedance. During Bus Write operations the Command Register does not use these
bits. When reading the Status Register these bits should be ignored.
Data Input/Output or Address Input (DQ15A-1)
When BYTE is High, V
When BYTE is Low, V
LSB of the Word on the other addresses, DQ15A–1 High will select the MSB. Throughout
the text consider references to the Data Input/Output to include this pin when BYTE is High
and references to the Address Inputs to include this pin when BYTE is Low except when
stated explicitly otherwise.
Chip Enable
The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to
be performed. When Chip Enable is High, V
Output Enable
The Output Enable, G, controls the Bus Read operation of the memory.
Figure 1.: Logic Diagram
IL
IH
, this pin behaves as an address pin; DQ15A–1 Low will select the
, this pin behaves as a Data Input/Output pin (as DQ8-DQ14).
and
IH
. When BYTE is Low, V
Table 1.: Signal
IH
, all other pins are ignored.
Names, for a brief overview of the signals
IL
, these pins are not used and are