M29F400FB55M3F2 Micron Technology Inc, M29F400FB55M3F2 Datasheet - Page 23

• Manufacturer Part Number: M29F400FB55M3F2
• Manufacturer: Micron Technology Inc

Specifications of M29F400FB55M3F2

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 55ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 19/18Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 125C
• Package Type: SO W
• Program/erase Volt (typ): 4.5 to 5.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Automotive
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 512K/256K
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Compliant

3
3.1
3.2
3.3
3.4
Bus Operations
There are five standard bus operations that control the device. These are Bus Read, Bus
Write, Output Disable, Standby and Automatic Standby. See
BYTE = VIL
less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect
bus operations.
Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command
Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, V
Enable High, V
AC Waveforms
becomes valid.
Bus Write
Bus Write operations write to the Command Interface. A valid Bus Write operation begins by
setting the desired address on the Address Inputs. The Address Inputs are latched by the
Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V
during the whole Bus Write operation. See the following figures and tables:
Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V
Standby
When Chip Enable is High, V
Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to
the Standby Supply Current, I
Standby current level see
During program or erase operations the memory will continue to use the Program/Erase
Supply Current, I
Figure 21.: Write AC Waveforms, Write Enable Controlled
Figure 22.: Write AC Waveforms, Chip Enable
Table 16.: Write AC Characteristics, Write Enable Controlled
Table 17.: Write AC Characteristics, Chip Enable
and
IH
and
. The Data Inputs/Outputs will output the value, see
Table 3.: Bus Operations, BYTE = VIH
CC3
Table 15.: Read AC
, for Program or Erase operations until the operation completes.
Table 14.: DC
IH
CC2
, the memory enters Standby mode and the Data
IL
, Chip Enable should be held within V
, to Chip Enable and Output Enable and keeping Write
Characteristics.
Characteristics, for details of when the output
Controlled,
Controlled.
for a summary. Typically glitches of
Table 2.: Bus Operations,
Figure 20.: Read Mode
CC
± 0.2V. For the
23/67
IH
IH
.
,