M29F400FB55M3F2 Micron Technology Inc, M29F400FB55M3F2 Datasheet - Page 35

• Manufacturer Part Number: M29F400FB55M3F2
• Manufacturer: Micron Technology Inc

Specifications of M29F400FB55M3F2

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 55ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 19/18Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 125C
• Package Type: SO W
• Program/erase Volt (typ): 4.5 to 5.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Automotive
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 512K/256K
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Compliant

5.3
5.4
5.5
Error Bit
The Error Bit (DQ5) can be used to identify errors detected by the Program/Erase Controller.
The Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write
the correct data to the memory. If the Error Bit is set a Read/Reset command must be
issued before other commands are issued. The Error bit is output on DQ5 when the Status
Register is read.
Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to
do so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’.
One of the Erase commands must be used to set all the bits in a block or in the whole
memory from ’0’ to ’1’
Erase Timer Bit
The Erase Timer Bit (DQ3) can be used to identify the start of Program/Erase Controller
operation during a Block Erase command. Once the Program/Erase Controller starts
erasing the Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the
Erase Timer Bit is set to ’0’ and additional blocks to be erased may be written to the
Command Interface. The Erase Timer Bit is output on DQ3 when the Status Register is
read.
Alternative Toggle Bit
The Alternative Toggle Bit (DQ2) can be used to monitor the Program/Erase controller
during Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status
Register is read.
During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’,
etc., with successive Bus Read operations from addresses within the blocks being erased.
A protected block is treated the same as a block not being erased. Once the operation
completes the memory returns to Read mode.
During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with
successive Bus Read operations from addresses within the blocks being erased. Bus Read
operations to addresses within blocks not being erased will output the memory cell data as if
in Read mode.
After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be
used to identify which block or blocks have caused the error. The Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses
within blocks that have not erased correctly. The Alternative Toggle Bit does not change if
the addressed block has erased correctly.
35/67