ATMEGA328P-20PU Atmel, ATMEGA328P-20PU Datasheet - Page 131
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ATMEGA328P-20PU
Manufacturer Part Number
ATMEGA328P-20PU
Description
Manufacturer
Atmel
Datasheet
1.ATMEGA328P-20PU.pdf
(419 pages)
Specifications of ATMEGA328P-20PU
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
SPI/TWI/USART
Program Memory Type
Flash
Program Memory Size
32KB
Total Internal Ram Size
2KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
6-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
28
Package Type
PDIP
Lead Free Status / Rohs Status
Compliant
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15.11 Register Description
15.11.1
8025K–AVR–10/09
TCCR1A – Timer/Counter1 Control Register A
Figure 15-13
Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (f
• Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A
• Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B
The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respec-
tively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output
overrides the normal port functionality of the I/O pin it is connected to. If one or both of the
COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-
ing to the OC1A or OC1B pin must be set in order to enable the output driver.
When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is depen-
dent of the WGM13:0 bits setting.
WGM13:0 bits are set to a Normal or a CTC mode (non-PWM).
Table 15-1.
Bit
(0x80)
Read/Write
Initial Value
COM1A1/COM1B1
and ICF n
(PC and PFC PWM)
TOVn
(CTC and FPWM)
(Update at TOP)
0
0
1
1
OCRnx
TCNTn
TCNTn
as TOP)
(clk
clk
clk
I/O
(FPWM)
shows the same timing data, but with the prescaler enabled.
I/O
Tn
/8)
COM1A1
(if used
Compare Output Mode, non-PWM
R/W
7
0
COM1A0
COM1A0/COM1B0
R/W
6
0
TOP - 1
TOP - 1
Old OCRnx Value
0
1
0
1
COM1B1
R/W
Table 15-1
5
0
COM1B0
R/W
4
0
Description
Normal port operation, OC1A/OC1B disconnected.
Toggle OC1A/OC1B on Compare Match.
Clear OC1A/OC1B on Compare Match (Set output to
low level).
Set OC1A/OC1B on Compare Match (Set output to
high level).
shows the COM1x1:0 bit functionality when the
TOP
TOP
ATmega48P/88P/168P
R
3
0
–
BOTTOM
TOP - 1
clk_I/O
R
2
0
–
New OCRnx Value
/8)
WGM11
R/W
1
0
BOTTOM + 1
TOP - 2
WGM10
R/W
0
0
TCCR1A
131
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