MC68HC908LD60IFU Freescale Semiconductor, MC68HC908LD60IFU Datasheet - Page 134

• Manufacturer Part Number: MC68HC908LD60IFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908LD60IFU

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 6MHz
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 6-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Compliant

Monitor ROM (MON)
10.4.1 Entering Monitor Mode
Technical Data
134
NOTE:
NOTE:
Table 10-1
specified in the table, monitor mode may be entered after a power-on
reset (POR) and will allow communication at 9600 baud provided one of
the following sets of conditions is met:
Holding the PTC3 pin low when entering monitor mode by a high voltage
causes a bypass of a divide-by-two stage at the oscillator. The OSCOUT
frequency is equal to the OSCXCLK frequency, and the OSC1 input
directly generates internal bus clocks. In this case, the OSC1 signal
must have a 50% duty cycle at maximum bus frequency.
If the reset vector is blank and monitor mode is entered, the chip will see
an additional reset cycle after the initial POR reset. Once the part has
been programmed, the traditional method of applying a high voltage,
V
Enter monitor mode with the pin configuration shown in
a reset. The rising edge of reset latches monitor mode. Once monitor
mode is latched, the values on the specified pins can change.
Once out of reset, the MCU monitor mode firmware then sends a break
signal (10 consecutive logic zeros) to the host computer, indicating that
it is ready to receive a command. The break signal also provides a timing
reference to allow the host to determine the necessary baud rate.
TST
1. If monitor entry is by high voltage on IRQ (IRQ = V
2. If monitor entry is by blank reset vector ($FFFE and $FFFF both
, to IRQ must be used to enter monitor mode.
– The external clock is 4.9152 MHz with PTC3 low or
contain $FF; erased state):
– The external clock is 9.8304 MHz
9.8304 MHz with PTC3 high
shows the pin conditions for entering monitor mode. As
Monitor ROM (MON)
MC68HC908LD60
Freescale Semiconductor
Table 10-1
TST
)
—
Rev. 1.1
after