MC68HC908LD60IFU Freescale Semiconductor, MC68HC908LD60IFU Datasheet - Page 244

• Manufacturer Part Number: MC68HC908LD60IFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908LD60IFU

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 6MHz
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 6-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Compliant

Input/Output (I/O) Ports
17.6 Port D
17.6.1 Port D Data Register
Technical Data
244
Alternative Function:
Address:
Port D is an 8-bit special-function port that shares two of its pins with the
multi-master IIC (MMIIC) module, two of its pins with the DDC12AB
module, and four of its pins with the sync processor.
The port D data register (PTD) contains a data latch for each of the eight
port D pins.
PTD[7:0] — Port D Data Bits
IICSDA, IICSCL — Multi-master IIC Data and Clock pins
DDCSCL, DDCSDA — DDC12AB Data and Clock pins
Reset:
Read:
Write:
These read/write bits are software-programmable. Data direction of
each port D pin is under the control of the corresponding bit in data
direction register D. Reset has no effect on port D data.
The PTD7/IICSDA and PTD6/IICSCL pins are multi-master IIC data
and clock pins. When the IICDATE and IICSCLE bits in the port D
control register (PDCR) are clear, the PTD7/IICSDA and
PTD6/IICSCL pins are available for general-purpose I/O.
(See
The PTD4/DDCSCL and PTD5/DDCSDA pins are DDC12AB clock
and data pins respectively. When the DDCSCLE and DDCDATE bits
in the port D control register (PDCR) are clear, the PTD4/DDCSCL
and PTD5/DDCSDA pins are available for general-purpose I/O. (See
17.6.3 Port D
IICSDA
$0003
PTD7
17.6.3 Port D
Bit 7
Figure 17-13. Port D Data Register (PTD)
Input/Output (I/O) Ports
IICSCL
PTD6
Options.)
6
Options.)
DDCSDA DDCSCL
PTD5
5
Unaffected by reset
PTD4
4
HOUT
PTD3
3
MC68HC908LD60
VOUT
PTD2
Freescale Semiconductor
2
PTD1
DE
1
—
Rev. 1.1
DCLK
PTD0
Bit 0