MC68HC908LD60IFU Freescale Semiconductor, MC68HC908LD60IFU Datasheet - Page 75

• Manufacturer Part Number: MC68HC908LD60IFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908LD60IFU

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 6MHz
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 6-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Compliant

MC68HC908LD60
Freescale Semiconductor
NOTE:
—
Rev. 1.1
I — Interrupt Mask
To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.
N — Negative flag
Z — Zero flag
When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.
After the I bit is cleared, the highest-priority interrupt request is
serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack and restores the interrupt mask from the stack. After any
reset, the interrupt mask is set and can be cleared only by the clear
interrupt mask software instruction (CLI).
The CPU sets the negative flag when an arithmetic operation, logic
operation, or data manipulation produces a negative result, setting bit
7 of the result.
The CPU sets the zero flag when an arithmetic operation, logic
operation, or data manipulation produces a result of $00.
1 = Interrupts disabled
0 = Interrupts enabled
1 = Negative result
0 = Non-negative result
1 = Zero result
0 = Non-zero result
Central Processor Unit (CPU)
Central Processor Unit (CPU)
CPU Registers
Technical Data
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