MC68HC908LD60IFU Freescale Semiconductor, MC68HC908LD60IFU Datasheet - Page 190

• Manufacturer Part Number: MC68HC908LD60IFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908LD60IFU

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 6MHz
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 6-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Compliant

Multi-Master IIC Interface (MMIIC)
14.5.5 Multi-Master IIC Data Transmit Register (MMDTR)
Technical Data
190
Address:
MMTXBE — Multi-Master Transmit Buffer Empty
MMRXBF — Multi-Master Receive Buffer Full
When the MMIIC module is enabled, MMEN = 1, data written into this
register depends on whether module is in master or slave mode.
In slave mode, the data in MMDTR will be transferred to the output circuit
when:
Reset:
Read:
Write:
Figure 14-6. Multi-Master IIC Data Transmit Register (MMDTR)
This flag indicates the status of the data transmit register (MMDTR).
When the CPU writes the data to the MMDTR, the MMTXBE flag will
be cleared. MMTXBE is set when MMDTR is emptied by a transfer of
its data to the output circuit. Reset sets this bit.
This flag indicates the status of the data receive register (MMDRR).
When the CPU reads the data from the MMDRR, the MMRXBF flag
will be cleared. MMRXBF is set when MMDRR is full by a transfer of
data from the input circuit to the MMDRR. Reset clears this bit.
•
•
1 = Data transmit register empty
0 = Data transmit register full
1 = Data receive register full
0 = Data receive register empty
the module detects a matched calling address (MMATCH = 1),
with the calling master requesting data (MMSRW = 1); or
the previous data in the output circuit has be transmitted and the
receiving master returns an acknowledge bit, indicated by a
received acknowledge bit (MMRXAK = 0).
MMTD7
$006E
Bit 7
Multi-Master IIC Interface (MMIIC)
1
MMTD6
6
1
MMTD5
5
1
MMTD4
4
1
MMTD3
3
1
MC68HC908LD60
MMTD2
Freescale Semiconductor
2
1
MMTD1
1
1
—
MMTD0
Rev. 1.1
Bit 0
1