UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 188

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

<R>
(10) Edge detection
(11) STOP mode or main system clock stop mode setting
186
<1> If the TI00n pin or the TI01n pin is high level immediately after system reset and the rising edge or both
<2> The sampling clock used to eliminate noise differs when the valid edge of the TI00n pin is used as the count
Except when the TI00n, TI01n pin input is selected, stop the timer operation before setting STOP mode or main
system clock stop mode; otherwise the timer may malfunction when the main system clock starts.
Remark n = 0, 1
the rising and falling edges are specified as the valid edge for the TI00n pin or TI01n pin to enable 16-bit
timer counter 0n (TM0n) operation, a rising edge is detected immediately. Be careful when pulling up the
TI00n pin or the TI01n pin. However, the rising edge is not detected if the TI00n pin or the TI01n pin is
high level at restart after the operation has been stopped.
clock and when it is used as a capture trigger. In the former case, the count clock is f
case the count clock is selected by prescaler mode register 0n (PRM0n). The capture operation is not
performed until the valid edge is sampled and the valid level is detected twice, thus eliminating noise with
a short pulse width.
CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01
User’s Manual U14260EJ4V0UD
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, and in the latter