UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 355

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

18.5.6 Wait
receive data (i.e., is in a wait state).
canceled for both the master and slave devices, the next data transfer can begin.
The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or
Setting the SCL0 pin to low level notifies the communication partner of the wait status. When wait status has been
Transfer lines
(1) When master device has a nine-clock wait and slave device has an eight-clock wait
Master
Slave
ACKE0
SDA0
SCL0
SCL0
SCL0
IIC0
IIC0
CHAPTER 18 SERIAL INTERFACE IIC0 ( PD780078Y SUBSERIES ONLY)
H
(master transmits, slave receives, and ACKE0 = 1)
D2
6
6
D1
7
7
Master returns to high
impedance but slave
is in wait state (low level).
Wait after output
of eighth clock
User’s Manual U14260EJ4V0UD
Figure 18-16. Wait (1/2)
D0
8
8
9
Wait from
slave
ACK
9
FFH is written to IIC0 or WREL0 is set to 1
Wait after output
of ninth clock
Wait from
master
IIC0 data write (cancel wait)
D7
1
1
D6
2
2
D5
3
3
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