UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 220

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

11.4 Watchdog Timer Operations
11.4.1 Watchdog timer operation
detect a program loop.
register (WDCS). The watchdog timer starts by setting bit 7 (RUN) of WDTM to 1. After the watchdog timer is started,
set RUN to 1 within the set loop time interval. The watchdog timer can be cleared and counting started by setting
RUN to 1.
is generated according to the value of bit 3 (WDTM3) of WDTM.
before the STOP mode is set, clear the watchdog timer and then execute the STOP instruction.
218
When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to
The loop detection time interval is selected with bits 0 to 2 (WDCS0 to WDCS2) of the watchdog timer clock select
If RUN is not set to 1 and the loop detection time is exceeded, system reset or a non-maskable interrupt request
The watchdog timer continues operating in the HALT mode but it stops in the STOP mode. Thus, set RUN to 1
Cautions 1. The actual loop detection time may be shorter than the set time by up to 2
Note Expanded-specification products of PD780078 Subseries only.
Remark f
2. When the subsystem clock is selected for the CPU clock, the watchdog timer count operation
X
: Main system clock oscillation frequency
is stopped.
2
2
2
2
2
2
2
2
Loop Detection Time
12
13
14
15
16
17
18
20
/f
/f
/f
/f
/f
/f
/f
/f
X
X
X
X
X
X
X
X
Table 11-2. Watchdog Timer Loop Detection Time
CHAPTER 11 WATCHDOG TIMER
User’s Manual U14260EJ4V0UD
488 s
977 s
1.95 ms
3.91 ms
7.82 ms
15.6 ms
31.2 ms
125 ms
When Operated at
f
X
= 8.38 MHz
341 s
682 s
1.36 ms
2.73 ms
5.46 ms
10.9 ms
21.8 ms
87.3 ms
When Operated at
f
X
= 12 MHz
Note
8
/f
X
seconds.