UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 364

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

18.5.15 Communication operations
(1) Master operations
362
The procedure of controlling slave EEPROM
is as follows.
PM32, PM33
Set port (mode and data).
Set IIC control register 0.
Issue stop condition.
Issue start condition.
IICE0 = WTIM0 = 1
IICIF0, IICMK0
Set transfer clock.
PM32, PM33
IICCL0
Set interrupt.
SPD0 = 1?
CHAPTER 18 SERIAL INTERFACE IIC0 ( PD780078Y SUBSERIES ONLY)
SPT0 = 1
STT0 = 1
Set port.
START
A
1, P32, P33
Yes
H
0
0
Figure 18-21. Master Operation Flowchart (1/5)
0
No
User’s Manual U14260EJ4V0UD
TM
using the PD780078Y Subseries as the master of the I
Set the port that functions alternately as the
pins to be used. First set the port in the input
mode, and clear the output latch to 0.
Specify the operation mode, turn on/off the
digital filter, and specify the transfer rate.
Set a 9-clock wait and enable operation.
Set the port in the output mode to enable
output of I
Clear the interrupt request of I
Clear the mask to enable the interrupt when
using the interrupt.
Issue the stop condition before starting
operation, and release the bus.
First perform initialization to use I
Wait until the bus is released.
If the stop condition is detected, the bus is
released and can be used. Declare use of
the bus by issuing the start condition.
If the stop condition cannot be detected, the
chances are the connected pin is driving the
bus low.
In this case, refer to Remark.
2
C.
2
C.
2
C.
2
C bus