UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 486

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

484
Caution
Remarks 1.
CHAPTER 25 ELECTRICAL SPECIFICATIONS (EXPANDED-SPECIFICATION PRODUCTS OF PD780076, 780078, 78F0078)
ASTB high-level width
Address setup time
Address hold time
Input time from address to data
Output time from RD to address
Input time from RD to data
Read data hold time
RD low-level width
Input time from RD to WAIT
Input time from WR to WAIT
WAIT low-level width
Write data setup time
Write data hold time
WR low-level width
Delay time from ASTB to RD
Delay time from ASTB to WR
Delay time from
RD to ASTB at external fetch
Hold time from
RD to address at external fetch
Write data output time from RD
Write data output time from WR
Hold time from WR to address
Delay time from WAIT to RD
Delay time from WAIT to WR
(2) Read/write operation (T
T
2.
3.
Parameter
CY
can only be used when the MIN. value is 0.4 s.
t
n indicates the number of waits.
C
ASTB pins.)
CY
L
= 100 pF (C
= T
CY
/4
L
indicates the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and
A
= –40 to +85 C, V
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
WRADH
t
t
t
t
t
t
t
t
RDWT1
RDWT2
t
ASTWR
RDADH
t
t
ASTRD
RDAST
WRWD
t
t
t
RDWD
WTRD
WTWR
t
RDAD
WRWT
WRL1
ASTH
ADD1
ADD2
RDD1
RDD2
RDL1
RDL2
WDS
WDH
ADS
ADH
RDH
WTL
User’s Manual U14260EJ4V0UD
Conditions
DD
= 2.7 to 4.0 V)
(1.5 + 2n)t
(2.5 + 2n)t
(0.5 + 2n)t
(1.5 + 2n)t
0.8t
0.8t
0.8t
2t
0.3t
0.5t
0.5t
CY
MIN.
CY
30
10
60
10
10
CY
40
20
CY
0
0
– 30
CY
CY
CY
– 30
– 30
– 30
CY
CY
CY
CY
– 40
– 40
+ 10
– 30
(2 + 2n)t
(3 + 2n)t
(2 + 2n)t
(3 + 2n)t
1.2t
1.2t
2.5t
2.5t
(2 + 2n)t
t
t
t
CY
CY
CY
1.2t
MAX.
200
120
CY
CY
CY
CY
– 75
– 60
– 50
CY
CY
CY
CY
CY
+ 60
+ 60
+ 50
+ 50
– 108
– 120
– 148
– 162
CY
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2/3)