UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 295

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

T
Remarks 1. <1> to <6> in this table correspond to <1> to <6> in Figure 15-16.
X
Read ASIF2 (to confirm TXBF = 0)
and write data (n).
Read ASIF2 (to confirm TXBF = 0).
No data to be written.
Read ASIF2 (to confirm TXBF = 0)
and clear POWER2 or TXE2.
D2 (output)
INTST2
TXB2
TXS2
TXBF
TXSF
Transmission Procedure
2. TXBF:
<1>
TXSF:
POWER2: Bit 7 of asynchronous serial interface mode register 2 (ASIM2)
TXE2:
Data (n
Figure 15-16. Timing of Completing Successive Transmission
Data
transfer
Table 15-8. Timing of Completing Successive Transmission
Parity
<2>
Stop
1)
Bit 1 (transmit buffer data flag) of asynchronous serial interface transmission status
register 2 (ASIF2)
Bit 0 of ASIF2 (transmit shift register data flag)
Bit 6 of ASIM2
Start
CHAPTER 15 SERIAL INTERFACE UART2
Data (n
Data (n
User’s Manual U14260EJ4V0UD
Data (n)
<3>
<1> Data (n–2) is transmitted.
<2> Interrupt (INTST2) occurs.
<3> Generates start bit and starts
(during transmission)
<4> Interrupt (INTST2) occurs.
<5> Generates start bit and starts
(during transmission)
<6> Interrupt (INTST2) occurs.
Initializes internal circuit.
1)
1)
transmitting data (n–1).
transmitting data (n).
Data
transfer
Parity
Internal Operation
<4>
Stop
Start
Data (n
Data (n)
<5>
1)
Parity
TXBF
<6>
1
0
1
0
1
0
Stop
FF
FF
POWER2 or
TXE2 is cleared.
TXSF
1
1
1
1
1
0
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