UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 404

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

(1) Interrupt request flag registers (IF0L, IF0H, IF1L)
402
Address: FFE0H After reset: 00H R/W
Symbol
IF0L
Address: FFE1H After reset: 00H R/W
Symbol
IF0H
Address: FFE2H After reset: 00H R/W
Symbol
IF1L
An interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is
executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon
RESET input.
When an interrupt is acknowledged, the interrupt request flag is automatically cleared, and then the interrupt
routine is executed.
IF0L, IF0H, and IF1L are set by a 1-bit or 8-bit memory manipulation instruction. When IF0L and IF0H are
combined to form 16-bit register IF0, they are read by a 16-bit memory manipulation instruction.
RESET input clears IF0L, IF0H, and IF1L to 00H.
Note
Cautions 1. The WDTIF flag is R/W enabled only when the watchdog timer is used as an interval timer.
Incorporated only in the PD780078Y Subseries. Be sure to set 0 for the PD780078 Subseries.
2. When operating a timer, serial interface, or A/D converter after standby release, operate it
3. When manipulating a flag of the interrupt request flag register, use a 1-bit memory
TMIF011
TMIF51
XXIFX
Figure 19-2. Format of Interrupt Request Flag Register (IF0L, IF0H, IF1L)
STIF0
If watchdog timer mode 1 is used, set the WDTIF flag to 0.
after clearing the interrupt request flag, because interrupt request flags may be set by noise.
manipulation instruction (CLR1). When describing in C language, use a bit manipulation
instruction such as “IF0L.0 = 0;” or “_asm(“clr1 IF0L, 0”);” because the compiled assembler
must be a 1-bit memory manipulation instruction (CLR1).
If a program is described in C language using an 8-bit memory manipulation instruction
such as “IF0L &= 0xfe;” and compiled, it becomes the assembler of three instructions.
In this case, even if the request flag of another bit of the same interrupt request flag register
(IF0L) is set to 1 at the timing between “mov a, IF0L” and “mov IF0L, a”, the flag is cleared
to 0 at “mov IF0L, a”. Therefore, care must be exercised when using an 8-bit memory
manipulation instruction in C language.
7
7
7
0
1
mov a, IF0L
and a, #0FEH
mov IF0L, a
No interrupt request signal is generated
Interrupt request signal is generated, interrupt request status
TMIF001
TMIF50
SRIF0
6
6
6
CHAPTER 19 INTERRUPT FUNCTIONS
TMIF010
SERIF0
STIF2
5
5
5
User’s Manual U14260EJ4V0UD
TMIF000
SRIF2
PIF3
4
4
4
Interrupt request flag
SERIF2
WTIIF0
PIF2
3
3
3
IICIF0
KRIF
PIF1
2
2
2
Note
CSIIF3
WTIF
PIF0
1
1
1
WDTIF
CSIIF1
ADIF0
0
0
0